The present invention relates to semiconductor devices and methods for fabricating the devices, and particularly relates to semiconductor devices including fully-silicided gate electrodes and methods for fabricating the devices.
With recent increase in the integration degree and speed of semiconductor integrated circuit devices and expansion of the functionality thereof, studies using metal materials for gate electrodes have been intensively conducted. As candidates for metal materials, metal nitride, dual metal made of two types of pure metals having different work functions and fully-silicided (FUSI) materials formed by changing whole silicon into metal silicide are known. Among these, attention is given on FUSI materials as a promising technique because current silicon processing techniques are still used for the FUSI materials.
A structure of a metal-oxide-semiconductor field effect transistor (MOSFET) using full silicidation and a method for the MOSFET is disclosed in D. Aime et al., IEDM Tech. Digest, p. 87 (2004) and J. A. Kittl et al., Symp. of VLSI Technology, p. 72 (2005).
FIG. 16 illustrates a cross-sectional structure of a conventional semiconductor device including a FUSI gate electrode structure. FIGS. 17A through 17D illustrate cross-sectional structures in respective process steps of a method for fabricating the semiconductor device illustrated in FIG. 16 in the order of fabrication.
The method for fabricating the conventional FUSI semiconductor device will be described. First, as illustrated in FIG. 17A, an isolation region 2 is selectively formed in an upper portion of a semiconductor substrate 1 of silicon to electrically separate elements (i.e., transistors). Then, a p-well 3 is formed by ion implantation in an upper portion of the semiconductor substrate 1. Subsequently, a gate insulating film 4 is formed on the semiconductor substrate 1, and then a polysilicon film 5 forming a gate electrode and a silicon oxide film 6 protecting the polysilicon film 5 are deposited in this order on the gate insulating film 4. Thereafter, photolithography and dry etching are performed, thereby patterning the gate insulating film 4, the polysilicon film 5 and the silicon oxide film 6 so that a gate-electrode formation film 7 is formed out of the polysilicon film 5 and the silicon oxide film 6. Subsequently, ion implantation is performed using the gate-electrode formation film 7 as a mask, thereby forming shallow source/drain doped layers 8 in the p-well 3.
Next, as illustrated in FIG. 17B, an insulating film is deposited over the semiconductor substrate 1 to cover the gate-electrode formation film 7 and the deposited insulating film is etched back, thereby forming insulating sidewalls 9 on both sides of the gate-electrode formation film 7. Subsequently, ion implantation is performed using the gate-electrode formation film 7 and the sidewalls 9 as masks, thereby forming deep source/drain doped layers 10 in the p-well 3 below both sides of the gate-electrode formation film 7. Thereafter, a nickel film (not shown) is deposited over the semiconductor substrate 1 and then is subjected to annealing, thereby causing silicon forming the deep source/drain doped layers 10 in the semiconductor substrate 1 and the nickel film in contact with this silicon portion to react with each other. Accordingly, silicon regions in upper portions of the source/drain doped layers 10 are silicided. Thereafter, an unreacted portion of the nickel film is removed, thereby selectively forming nickel silicide layers 11 in the upper portions of the source/drain doped layers 10. Then, an interlayer insulating film 12 made of silicon oxide is deposited over the semiconductor substrate 1. Thereafter, the interlayer insulating film 12 is planalized by chemical mechanical polishing (CMP) so that the surface of the interlayer insulating film 12 is at the same level as the upper ends of the sidewalls 9.
Then, as illustrated in FIG. 17C, the silicon oxide film 6 is etched so that the polysilicon film 5 under the silicon oxide film 6 is exposed. Subsequently, a metal film 13 made of, for example, nickel is deposited over the interlayer insulating film 12, the sidewalls 9 and the polysilicon film 5 exposed between the sidewalls 9.
Thereafter, as illustrated in FIG. 17D, annealing is performed to cause a reaction between the polysilicon film 5 included in the gate-electrode formation film and the metal film 13 in contact with the polysilicon film 5, thereby forming a FUSI gate electrode 14 made of nickel silicide. In this manner, the conventional semiconductor device illustrated in FIG. 16 is completed.
As a result of full silicidation of the gate electrode 14 described above, the resistance of the gate electrode 14 is reduced, and the device is allowed to operate at higher speed.
However, the conventional semiconductor device and the conventional method for fabricating the device have a problem in which the gate electrode is not fully silicided and unreacted polysilicon remains if a FUSI electrode whose gate length or gate area is large is used as the gate electrode 14. In addition, there also arises another problem in which the metal film 13 and the polysilicon film 5 forming the gate-electrode formation film 7 excessively react with each other to form silicide having partially different compositions in the gate electrode.
FIGS. 18A and 18B illustrate problems occurring in the FUSI gate electrode 14. In FIG. 18A, a transistor in a first region A is a transistor having a relatively small gate length (gate area) and is, for example, a transistor forming an internal circuit such as a logic circuit or a static random access memory (SRAM) circuit. On the other hand, a transistor in a second region B is a transistor having a gate length (gate area) larger than that of the transistor in the first region A and is, for example, a transistor forming an input/output circuit.
As illustrated in FIG. 18A, in depositing the metal film 13 over the exposed polysilicon film 5, tMetal/tSi, which is the ratio of the thickness tMetal of the metal film to the thickness tSi of the polysilicon film 5 in a middle portion of the gate electrode in the second region B, is smaller than tMetal/tSi, which is the ratio of the thickness tMetal of the metal film to the thickness tSi of the polysilicon film 5 in the first region A. This is conspicuous when the value twice as large as the gate length in the first region A is smaller than the thickness of the metal film 13 and the value twice as large as the gate length in the second region B is larger than the thickness of the metal film 13.
As a result, as illustrated in FIG. 18B, the gate electrode 14A in the first region A is fully silicided, whereas the metal film 13 is insufficiently supplied in a middle portion of the polysilicon film 5 in the second region B because of the large gate length or area of the gate electrode 14B. Accordingly, as illustrated in FIG. 18B, an unreacted region 5a is likely to be formed in a middle lower portion of the polysilicon film 5. If such an unreacted region 5a is formed in the gate electrode 14B, characteristics such as the threshold voltage vary, so that desired transistor characteristics are not obtained.
In addition, the metal film 13 is also deposited on the inner walls of the sidewalls 9 in the second region B, so that the thickness of the metal film 13 deposited on the inner walls is larger than that of the other part. Accordingly, metal is excessively supplied to portions of the polysilicon film 5 in contact with the sidewalls 9, so that metal-rich portions 16 having a silicide composition different from that in the middle portion of the gate electrode 14B are formed. If such metal-rich portions 16 are formed in the gate electrode 14B, the gate resistance varies and circuit operation is adversely affected.